A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator.

Ryota Sekimoto Akira Shikata Tadahiro Kuroda Hiroki Ishikuro A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator. 471-474 2011 ESSCIRC http://dx.doi.org/10.1109/ESSCIRC.2011.6045009 conf/esscirc/2011 db/conf/esscirc/esscirc2011.html#SekimotoSKI11