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BibTeX record conf/esscirc/BiswasC16
@inproceedings{DBLP:conf/esscirc/BiswasC16, author = {Avishek Biswas and Anantha P. Chandrakasan}, title = {A 0.36V 128Kb 6T {SRAM} with energy-efficient dynamic body-biasing and output data prediction in 28nm {FDSOI}}, booktitle = {{ESSCIRC} Conference 2016: 42\({}^{\mbox{nd}}\) European Solid-State Circuits Conference, Lausanne, Switzerland, September 12-15, 2016}, pages = {433--436}, publisher = {{IEEE}}, year = {2016}, url = {https://doi.org/10.1109/ESSCIRC.2016.7598334}, doi = {10.1109/ESSCIRC.2016.7598334}, timestamp = {Wed, 16 Oct 2019 14:14:53 +0200}, biburl = {https://dblp.org/rec/conf/esscirc/BiswasC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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