BibTeX record conf/esscirc/AyresRBFV16

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@inproceedings{DBLP:conf/esscirc/AyresRBFV16,
  author       = {A. Ayres and
                  Olivier Rozeau and
                  B. Borot and
                  Laurent Fesquet and
                  Maud Vinet},
  title        = {Delay partitioning helps reducing variability in 3DVLSI},
  booktitle    = {{ESSCIRC} Conference 2016: 42\({}^{\mbox{nd}}\) European Solid-State
                  Circuits Conference, Lausanne, Switzerland, September 12-15, 2016},
  pages        = {75--78},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/ESSCIRC.2016.7598246},
  doi          = {10.1109/ESSCIRC.2016.7598246},
  timestamp    = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl       = {https://dblp.org/rec/conf/esscirc/AyresRBFV16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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