BibTeX record conf/ecctd/BelliziaMT17

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@inproceedings{DBLP:conf/ecctd/BelliziaMT17,
  author       = {Davide Bellizia and
                  Pietro Monsurr{\`{o}} and
                  Alessandro Trifiletti},
  title        = {{VHDL} implementation of {FWL} {RLS} algorithm},
  booktitle    = {2017 European Conference on Circuit Theory and Design, {ECCTD} 2017,
                  Catania, Italy, September 4-6, 2017},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/ECCTD.2017.8093356},
  doi          = {10.1109/ECCTD.2017.8093356},
  timestamp    = {Sat, 09 Apr 2022 12:45:43 +0200},
  biburl       = {https://dblp.org/rec/conf/ecctd/BelliziaMT17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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