<?xml version="1.0"?>
<dblp>
<inproceedings key="conf/dsl/JenningsB99" mdate="2002-12-18">
<author>James Jennings</author>
<author>Eric Beuscher</author>
<title>Verischemelog: Verilog embedded in Scheme.</title>
<pages>123-134</pages>
<year>1999</year>
<booktitle>DSL</booktitle>
<ee>http://doi.acm.org/10.1145/331960.331978</ee>
<url>db/conf/dsl/dsl1999.html#JenningsB99</url>
</inproceedings>
</dblp>
