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@inproceedings{DBLP:conf/dsl/JenningsB99,
author = {James Jennings and
Eric Beuscher},
title = {Verischemelog: Verilog embedded in Scheme},
booktitle = {DSL},
year = {1999},
pages = {123-134},
ee = {http://doi.acm.org/10.1145/331960.331978},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Copyright © 2002-12-18 by Michael Ley (ley@uni-trier.de)