BibTeX record conf/dsd/WilleFMALD08

• > Home > conf/dsd/WilleFMALD08

@inproceedings{DBLP:conf/dsd/WilleFMALD08,
  author       = {Robert Wille and
                  G{\"{o}}rschwin Fey and
                  Marc Messing and
                  Gerhard Angst and
                  Lothar Linhard and
                  Rolf Drechsler},
  editor       = {Luca Fanucci},
  title        = {Identifying a Subset of System Verilog Assertions for Efficient Bounded
                  Model Checking},
  booktitle    = {11th Euromicro Conference on Digital System Design: Architectures,
                  Methods and Tools, {DSD} 2008, Parma, Italy, September 3-5, 2008},
  pages        = {542--549},
  publisher    = {{IEEE} Computer Society},
  year         = {2008},
  url          = {https://doi.org/10.1109/DSD.2008.53},
  doi          = {10.1109/DSD.2008.53},
  timestamp    = {Thu, 23 Mar 2023 23:59:37 +0100},
  biburl       = {https://dblp.org/rec/conf/dsd/WilleFMALD08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}