Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits.

Enrico Macii Leticia Maria Veiras Bolzani Andrea Calimera Alberto Macii Massimo Poncino Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. 298-303 2008 DSD http://dx.doi.org/10.1109/DSD.2008.90 conf/dsd/2008 db/conf/dsd/dsd2008.html#MaciiBCMP08