Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming.

Tun Li Yang Guo GongJie Liu Sikun Li Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming. 17-25 2005 conf/dsd/2005 DSD http://doi.ieeecomputersociety.org/10.1109/DSD.2005.43 db/conf/dsd/dsd2005.html#LiGLL05