A. Neslin Ismailoglu Murat Askar SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation. 566-571 2008 DSD http://dx.doi.org/10.1109/DSD.2008.117 conf/dsd/2008 db/conf/dsd/dsd2008.html#IsmailogluA08