Evaluating Dataflow and Pipelined Vector Processing Architectures for FPGA Co-processors.

Michael Freeman Evaluating Dataflow and Pipelined Vector Processing Architectures for FPGA Co-processors. 127-130 2006 conf/dsd/2006 DSD http://doi.ieeecomputersociety.org/10.1109/DSD.2006.51 db/conf/dsd/dsd2006.html#Freeman06