An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA.

Petr Fiser Pavel Kubalík Hana Kubatova An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA. 96-99 2008 DSD http://dx.doi.org/10.1109/DSD.2008.46 conf/dsd/2008 db/conf/dsd/dsd2008.html#FiserKK08