Chichyang Chen Liang-An Chen Jih-Ren Cheng Architectural Design of a Fast Floating-Point Multiplication-Add Fused Unit Using Signed-Digit Addition. 346-353 2001 conf/dsd/2001 DSD http://doi.ieeecomputersociety.org/10.1109/DSD.2001.952324 db/conf/dsd/dsd2001.html#ChenCC01