Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture.

Shervin Sharifi Mohammad Hosseinabady Pedram A. Riahi Zainalabedin Navabi Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture. 352-360 2003 conf/dft/2003 DFT http://csdl.computer.org/comp/proceedings/dft/2003/2042/00/20420352abs.htm db/conf/dft/dft2003.html#SharifiHRN03