BibTeX record conf/dft/SharifiHRN03

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@inproceedings{DBLP:conf/dft/SharifiHRN03,
  author       = {Shervin Sharifi and
                  Mohammad Hosseinabady and
                  Pedram A. Riahi and
                  Zainalabedin Navabi},
  title        = {Reducing Test Power, Time and Data Volume in SoC Testing Using Selective
                  Trigger Scan Architecture},
  booktitle    = {18th {IEEE} International Symposium on Defect and Fault-Tolerance
                  in {VLSI} Systems {(DFT} 2003), 3-5 November 2003, Boston, MA, USA,
                  Proceedings},
  pages        = {352--360},
  publisher    = {{IEEE} Computer Society},
  year         = {2003},
  url          = {https://doi.org/10.1109/DFTVS.2003.1250131},
  doi          = {10.1109/DFTVS.2003.1250131},
  timestamp    = {Fri, 24 Mar 2023 00:02:09 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/SharifiHRN03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}