Evaluation time Estimation for Pass Transistor Logic circuits.

P. W. Chandana Prasad Bruce Mills Ali Assi S. M. N. Arosha Senanayake V. C. Prasad Evaluation time Estimation for Pass Transistor Logic circuits. 422-428 2006 conf/delta/2006 DELTA http://doi.ieeecomputersociety.org/10.1109/DELTA.2006.47 db/conf/delta/delta2006.html#PrasadMASP06