BibTeX record conf/ddecs/CiesielskiYD22

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@inproceedings{DBLP:conf/ddecs/CiesielskiYD22,
  author       = {Maciej J. Ciesielski and
                  Atif Yasin and
                  Jiteshri Dasari},
  title        = {Functional Verification of Arithmetic Circuits: Survey of Formal Methods},
  booktitle    = {25th International Symposium on Design and Diagnostics of Electronic
                  Circuits and Systems, {DDECS} 2022, Prague, Czech Republic, April
                  6-8, 2022},
  pages        = {94--99},
  publisher    = {{IEEE}},
  year         = {2022},
  url          = {https://doi.org/10.1109/DDECS54261.2022.9770161},
  doi          = {10.1109/DDECS54261.2022.9770161},
  timestamp    = {Fri, 13 May 2022 16:17:42 +0200},
  biburl       = {https://dblp.org/rec/conf/ddecs/CiesielskiYD22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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