An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions.

Florence Azaïs Yves Bertrand Michel Renovell An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions. 158-163 2009 DDECS http://dx.doi.org/10.1109/DDECS.2009.5012119 conf/ddecs/2009 db/conf/ddecs/ddecs2009.html#AzaisBR09