ZhangZYZSPZCMSIC08'

@inproceedings{DBLP:conf/date/ZhangZYZSPZCMSIC08,
  author    = {Wanping Zhang and
               Yi Zhu and
               Wenjian Yu and
               Ling Zhang and
               Rui Shi and
               He Peng and
               Zhi Zhu and
               Lew Chua-Eoan and
               Rajeev Murgai and
               Toshiyuki Shibuya and
               Nuriyoki Ito and
               Chung-Kuan Cheng},
  title     = {Finding the Worst Voltage Violation in Multi-Domain Clock
               Gated Power Network},
  booktitle = {DATE},
  year      = {2008},
  pages     = {537-540},
  ee        = {http://dx.doi.org/10.1109/DATE.2008.4484906},
  crossref  = {DBLP:conf/date/2008},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

@proceedings{DBLP:conf/date/2008,
  title     = {Design, Automation and Test in Europe, DATE 2008, Munich,
               Germany, March 10-14, 2008},
  booktitle = {DATE},
  publisher = {IEEE},
  year      = {2008},
  isbn      = {978-3-9810801-3-1},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}