A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core.

Andreas Wortmann Sven Simon Matthias Müller A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core. 46-51 2004 conf/date/2004 DATE http://doi.ieeecomputersociety.org/10.1109/DATE.2004.1269197 db/conf/date/date2004-df.html#WortmannSM04