Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor.

Jun Wang Hongbo Zeng Kun Huang Ge Zhang Yan Tang Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor. 792-795 2008 DATE http://dx.doi.org/10.1109/DATE.2008.4484913 conf/date/2008 db/conf/date/date2008.html#WangZHZT08