A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context.

Anselme Vignon Stefan Cosemans Wim Dehaene Pol Marchal Marco Facchini A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context. 929-933 2009 DATE http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=5090609&arnumber=5090798&count=326&index=184 conf/date/2009 db/conf/date/date2009.html#VignonCDMF09