A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine.

Hisashi Sasaki A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine. 353- 1999 conf/date/1999 DATE http://csdl.computer.org/comp/proceedings/date/1999/0078/00/00780353abs.htm db/conf/date/date1999.html#Sasaki99