Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models.

Mukesh Ranjan Wim Verhaegen Anuradha Agarwal Hemanth Sampath Ranga Vemuri Georges G. E. Gielen Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. 604-609 2004 conf/date/2004 DATE http://csdl.computer.org/comp/proceedings/date/2004/2085/01/208510604abs.htm db/conf/date/date2004-1.html#RanjanVASVG04