@inproceedings{DBLP:conf/date/PullelaPDV98,
author = {Satyamurthy Pullela and
Rajendran Panda and
Abhijit Dharchoudhury and
Gopal Vija},
title = {CMOS Combinational Circuit Sizing by Stage-wise Tapering},
booktitle = {DATE},
year = {1998},
pages = {985-986},
ee = {http://doi.ieeecomputersociety.org/10.1109/DATE.1998.656001},
crossref = {DBLP:conf/date/1998},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
@proceedings{DBLP:conf/date/1998,
title = {1998 Design, Automation and Test in Europe (DATE '98), February
23-26, 1998, Le Palais des Congr{\`e}s de Paris, Paris,
France},
booktitle = {DATE},
publisher = {IEEE Computer Society},
year = {1998},
bibsource = {DBLP, http://dblp.uni-trier.de}
}