A methodology for FPGA to structured-ASIC synthesis and verification.

Michael Hutton Richard Yuan Jay Schleicher Gregg Baeckler Sammy Cheung Kar Keng Chua Hee Kong Phoo A methodology for FPGA to structured-ASIC synthesis and verification. 64-69 2006 conf/date/2006 DATE Designers' Forum http://doi.acm.org/10.1145/1131355.1131369 db/conf/date/date2006.html#HuttonYSBCCP06