BibTeX record conf/date/CoskunGJJKKMRSZ16

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@inproceedings{DBLP:conf/date/CoskunGJJKKMRSZ16,
  author       = {Ayse K. Coskun and
                  Anjun Gu and
                  Warren Jin and
                  Ajay Joshi and
                  Andrew B. Kahng and
                  Jonathan Klamkin and
                  Yenai Ma and
                  John Recchio and
                  Vaishnav Srinivas and
                  Tiansheng Zhang},
  editor       = {Luca Fanucci and
                  J{\"{u}}rgen Teich},
  title        = {Cross-layer floorplan optimization for silicon photonic NoCs in many-core
                  systems},
  booktitle    = {2016 Design, Automation {\&} Test in Europe Conference {\&}
                  Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016},
  pages        = {1309--1314},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://ieeexplore.ieee.org/document/7459512/},
  timestamp    = {Mon, 09 Aug 2021 01:32:18 +0200},
  biburl       = {https://dblp.org/rec/conf/date/CoskunGJJKKMRSZ16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}