Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design.

Youngchul Cho Ganghee Lee Sungjoo Yoo Kiyoung Choi Nacer-Eddine Zergainoh Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. 20132-20137 2003 conf/date/2003 DATE http://csdl.computer.org/comp/proceedings/date/2003/1870/02/187020132abs.htm db/conf/date/date2003.html#ChoLYCZ03