Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality.

Matthias Beck Olivier Barondeau Martin Kaibel Frank Poehl Xijiang Lin Ron Press Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality. 56-61 2005 conf/date/2005 DATE http://doi.ieeecomputersociety.org/10.1109/DATE.2005.199 db/conf/date/date2005.html#BeckBKPLP05