Efficient Testing of Clock Regenerator Circuits in Scan Designs.

Rajesh Raina Robert Bailey Charles Njinda Robert F. Molyneaux Charlie Beh Efficient Testing of Clock Regenerator Circuits in Scan Designs. 95-100 1997 DAC http://doi.acm.org/10.1145/266021.266042 db/conf/dac/dac97.html#RainaBNMB97