Three Competing Design Methodologies for ASIC's: Architectual Synthesis, Logic Synthesis, Logic Synthesis and Module Generation.

Kurt Keutzer Three Competing Design Methodologies for ASIC's: Architectual Synthesis, Logic Synthesis, Logic Synthesis and Module Generation. 308-313 1989 DAC http://doi.acm.org/10.1145/74382.74434 db/conf/dac/dac89.html#Keutzer89