Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction.

Yu Hu Yan Lin Lei He Tim Tuan Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction. 478-483 2006 conf/dac/2006 DAC http://doi.acm.org/10.1145/1146909.1147036 db/conf/dac/dac2006.html#HuLHT06