Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms.

Carlos Flores Fajardo Zhen Fang Ravi Iyer German Fabila Garcia Seung Eun Lee Li Zhao Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms. 966-971 2011 DAC http://doi.acm.org/10.1145/2024724.2024938 conf/dac/2011 db/conf/dac/dac2011.html#FajardoFIGLZ11