Enhancing timing-driven FPGA placement for pipelined netlists.

Kenneth Eguro Scott Hauck Enhancing timing-driven FPGA placement for pipelined netlists. 34-37 2008 DAC http://doi.acm.org/10.1145/1391469.1391480 conf/dac/2008 db/conf/dac/dac2008.html#EguroH08