FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation.

Scott Cromar Jaeho Lee Deming Chen FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation. 838-843 2009 DAC http://doi.acm.org/10.1145/1629911.1630125 conf/dac/2009 db/conf/dac/dac2009.html#CromarLC09