BibTeX record conf/dac/CongW97

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@inproceedings{DBLP:conf/dac/CongW97,
  author    = {Jason Cong and
               Chang Wu},
  title     = {{FPGA} Synthesis with Retiming and Pipelining for Clock Period Minimization
               of Sequential Circuits},
  booktitle = {{DAC}},
  pages     = {644--649},
  year      = {1997},
  url       = {http://doi.acm.org/10.1145/266021.266309},
  doi       = {10.1145/266021.266309},
  timestamp = {Mon, 16 Dec 2002 10:10:44 +0100},
  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/dac/CongW97},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}