Verification of VHDL Designs Using VAL.

Larry M. Augustin Benoit A. Gennart Youm Huh David C. Luckham Alec G. Stanculescu Verification of VHDL Designs Using VAL. 48-53 1988 DAC http://portal.acm.org/citation.cfm?id=285730.285737 db/conf/dac/dac88.html#AugustinGHLS88