Reducing Code Size by Graph Coloring Register Allocation and Assignment Algorithm for Mixed-Width ISA Processor.

Jyh-Shian Wang I-Wei Wu Yu-Sheng Chen Jean Jyh-Jiun Shann Wei-Chung Hsu Reducing Code Size by Graph Coloring Register Allocation and Assignment Algorithm for Mixed-Width ISA Processor. 174-181 2009 CSE (2) http://dx.doi.org/10.1109/CSE.2009.100 conf/cse/2009 db/conf/cse/cse2009-2.html#WangWCSH09