High-level synthesis for large bit-width multipliers on FPGAs: a case study.

Gang Quan James P. Davis Siddhaveerasharan Devarkal Duncan A. Buell High-level synthesis for large bit-width multipliers on FPGAs: a case study. 213-218 2005 conf/codes/2005 CODES+ISSS http://doi.acm.org/10.1145/1084834.1084890 db/conf/codes/codes2005.html#QuanDDB05