A modular simulation framework for architectural exploration of on-chip interconnection networks.

Tim Kogel Malte Doerper Andreas Wieferink Rainer Leupers Gerd Ascheid Heinrich Meyr Serge Goossens A modular simulation framework for architectural exploration of on-chip interconnection networks. 7-12 2003 conf/codes/2003 CODES+ISSS http://doi.acm.org/10.1145/944645.944648 db/conf/codes/codes2003.html#KogelDWLAMG03