BibTeX record conf/cicc/MathurKAAGWBTJZ22

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@inproceedings{DBLP:conf/cicc/MathurKAAGWBTJZ22,
  author       = {R. Mathur and
                  M. Kumar and
                  Vivek Asthana and
                  S. Aggarwal and
                  S. Gupta and
                  D. Wanjul and
                  A. Baradia and
                  S. Thota and
                  P. Jain and
                  B. Zheng and
                  A. Cubeta and
                  S. Thyagarajan and
                  A. Chen and
                  Y. K. Chong},
  title        = {5GHz {SRAM} for High-Performance Compute Platform in 5nm {CMOS}},
  booktitle    = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2022, Newport
                  Beach, CA, USA, April 24-27, 2022},
  pages        = {1--2},
  publisher    = {{IEEE}},
  year         = {2022},
  url          = {https://doi.org/10.1109/CICC53496.2022.9772840},
  doi          = {10.1109/CICC53496.2022.9772840},
  timestamp    = {Mon, 23 May 2022 16:36:21 +0200},
  biburl       = {https://dblp.org/rec/conf/cicc/MathurKAAGWBTJZ22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}