DPA Leakage Models for CMOS Logic Circuits.

Daisuke Suzuki Minoru Saeki Tetsuya Ichikawa DPA Leakage Models for CMOS Logic Circuits. 366-382 2005 conf/ches/2005 CHES http://dx.doi.org/10.1007/11545262_27 db/conf/ches/ches2005.html#SuzukiSI05