An Optimized S-Box Circuit Architecture for Low Power AES Design.

Sumio Morioka Akashi Satoh An Optimized S-Box Circuit Architecture for Low Power AES Design. 172-186 2002 conf/ches/2002 CHES http://link.springer.de/link/service/series/0558/bibs/2523/25230172.htm db/conf/ches/ches2002.html#MoriokaS02