Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm.

Henry Kuo Ingrid Verbauwhede Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm. 51-64 2001 conf/ches/2001 CHES http://link.springer.de/link/service/series/0558/bibs/2162/21620051.htm db/conf/ches/ches2001.html#KuoV01