CAIRN 2: An FPGA Implementation of the Sieving Step in the Number Field Sieve Method.

Tetsuya Izu Jun Kogure Takeshi Shimoyama CAIRN 2: An FPGA Implementation of the Sieving Step in the Number Field Sieve Method. 364-377 2007 conf/ches/2007 CHES http://dx.doi.org/10.1007/978-3-540-74735-2_25 db/conf/ches/ches2007.html#IzuKS07