Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs.

Ekawat Homsirikamol Marcin Rogawski Kris Gaj Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs. 491-506 2011 CHES http://dx.doi.org/10.1007/978-3-642-23951-9_32 conf/ches/2011 db/conf/ches/ches2011.html#HomsirikamolRG11