A Specification Methodology for the Optimal Layout of a 2-Stage Interconnect Bus for Massively Parallel Architectures.

Gerd Pfeiffer Manfred Schimmler A Specification Methodology for the Optimal Layout of a 2-Stage Interconnect Bus for Massively Parallel Architectures. 99-104 2008 CDES conf/cdes/2008 db/conf/cdes/cdes2008.html#PfeifferS08