Modeling and Realization of the Floating Point Inverse Square Root, Square Root, and Division unit (fP ISD) Using VHDL and FPGAs.

Jaafar Alghazo Modeling and Realization of the Floating Point Inverse Square Root, Square Root, and Division unit (fP ISD) Using VHDL and FPGAs. 39-45 2006 conf/cdes/2006 CDES db/conf/cdes/cdes2006.html#Alghazo06