AN ultra low power fault tolerant SRAM design in 90nm CMOS.

Kuande Wang Li Chen Jinsheng Yang AN ultra low power fault tolerant SRAM design in 90nm CMOS. 1076-1079 2009 CCECE http://dx.doi.org/10.1109/CCECE.2009.5090294 conf/ccece/2009 db/conf/ccece/ccece2009.html#WangCY09