Vectorized Symbolic Model Checking of Computation Tree Logic for Sequential Machine Verification.

Hiromi Hiraishi Kiyoharu Hamaguchi Hiroyuki Ochi Shuzo Yajima Vectorized Symbolic Model Checking of Computation Tree Logic for Sequential Machine Verification. 214-224 1991 conf/cav/1991 CAV db/conf/cav/cav91.html#HiraishiHOY91 http://dx.doi.org/10.1007/3-540-55179-4_21